• 100-500+ MHz fabric clocking
• 10G/40G/100G+ bps bandwidths
• Xilinx Virtex/Zynq/UltraScale families
• VHDL/Verilog
• DDR3/HMC Memory Links
• Design for Synthesis
• Computer Architecture Optimization
• Advanced Floorplanning
• Project Management and Documentation
• Timing and Performance Analysis

"A Practical Measure of FPGA Floating Point Acceleration for High Performance Computing"

Plublished for IEEE ASAP 2013

Read More...

As president and chief FPGA designer of Optimal Design, John Cappello has been creating high performance FPGA solutions for over 20 years in fields such as optical networks, high performance computing, broadband video, antenna measurement, medical imaging, and IP development. John uses his best engineering effort in combination with appropriate verification methods to develop reliable, high quality and cost-effective products. His skills with IP packaging, documentation and project management allow him to deliver FPGA products in a streamlined and user-friendly fashion.